The invention relates to a digital switching circuit which comprises first and second insulated gate field effect transistors, of which conduction channels located between main electrodes of the transistors are connected in series between a first and a second supply terminal. In operation the first transistor receives at its gate electrode a first control signal and the second transistor receives at its gate electrode a second control signal in a manner such that one of the transistors is rendered conducting and the other transistor is rendered non-conducting, the first control signal being an inverted version of the second control signal.
Such a circuit is known from the book "Large Scale Integration, Devices, Circuits and Systems", p. 276-277, published by "John Wiley and Sons Ltd.", New York 1981.
The circuit described in that book comprises a so-called "pushpull" output stage which comprises two transistors which are controlled by complementary signals D and D. The low value of the signal D or D to be received by one of the transistors may be substantially 0 V, in order that this transistor is kept in the non-conducting condition with certainty. If this transistor has now to be rendered conducting, the potential at the gate electrode of this transistor should be increased from 0 V until this transistor is "fully" conducting. This means that at each transition from "low" to "high" (from the non-conducting to the concucting state) a maximum signal should be supplied, which results in an associated inertia and excessive dissipation. However, it is possible to produce the voltage sweep from "low" to "high" by choosing the "low" level for example just below the threshold voltage of the transistor to be rendered non-conducting. However, the problem then arises that while the potential level of the gate electrode is "low" due to capacitive coupling to its surroundings the potential level of this gate electrode is disturbed (increased), the transistor then becoming conductive. Circuits in which data signals are supplied together with clock signals and the gate electrodes have a floating potential after termination of the clock signals are highly sensitive to capacitive cross-talk, the more so if the data signals supplied to the control inputs are assisted by means of the so-called bootstrap technique.